Intel, TSMC CPO Breakthrough Explained

The Silicon-Glass Hybrid Breakthrough: Intel & TSMC Unveil Co-packaged Optics (CPO) Milestones for 2026 Mass Production

1. Executive Summary: The Architecture of the Post-Copper Era

On December 28, 2025, the trajectory of the global semiconductor industry was fundamentally altered by a joint disclosure from Intel Corporation and Taiwan Semiconductor Manufacturing Company (TSMC). In a move that signifies the definitive conclusion of the "Copper Era" for high-performance computing (HPC), the two foundries released coordinated technical specifications for a unified Silicon-Glass Hybrid Platform. This announcement, detailed in technical briefings for Nature Electronics and IEEE Spectrum, confirms a synchronized roadmap to support mass production of Glass Substrate-based Co-packaged Optics (CPO) by the second half of 2026.1

For the past decade, the cadence of Moore’s Law has been increasingly decoupled from system performance. While transistor density continued to double, the "I/O Wall"—the physical inability of copper interconnects to move data in and out of chips at commensurate speeds without thermal ruin—became the primary bottleneck. As Artificial Intelligence (AI) models scaled from billions to trillions of parameters, the energy required effectively to transport data began to eclipse the energy used to process it. The industry encountered the "skin effect" at high frequencies, where signals traversing copper traces degrade rapidly, necessitating power-hungry Digital Signal Processors (DSPs) that consume up to 40% of a data center's power budget.3

The breakthrough announced by Intel and TSMC resolves this existential crisis through a radical material and architectural shift. By replacing the traditional organic resin substrate with a Glass Core Substrate and integrating Co-packaged Optics (CPO) directly adjacent to the compute die, the new platform achieves two critical performance thresholds required for the next generation of AI infrastructure:

1. 8x Increase in Bandwidth Density: The platform enables data transfer rates exceeding 100 Terabits per second (Tbps) per package, a figure unattainable with traditional electrical interconnects.5

2. 40% Reduction in Energy per Bit: By eliminating long-reach copper traces, energy consumption drops from approximately 15 picojoules per bit (pJ/bit) in conventional pluggable optics to less than 5 pJ/bit.3

This report offers an exhaustive analysis of this technological inflection point. We dissect the physics driving the transition from organic to glass substrates, the architectural revolution of CPO, the manufacturing supply chain implications for the 2026 production window, and the resulting investment landscape for the companies supplying the materials and components of the "Glass Era."

2. The Physics of the Barrier: The I/O and Power Wall

To fully comprehend the magnitude of the Intel-TSMC announcement, one must first deconstruct the physical barriers that necessitated it. The semiconductor industry is currently engaged in a battle against two intertwined adversaries: Signal Integrity (SI) degradation and Power Density constraints. These are not merely engineering hurdles but fundamental limits of physics that dictate the performance ceiling of modern computing.

2.1 The Skin Effect and Dielectric Loss

For decades, the foundation of semiconductor packaging has been the "organic" substrate—essentially an advanced, multi-layered Printed Circuit Board (PCB) composed of fiberglass and resin, known technically as FR4 or ABF (Ajinomoto Build-up Film). Copper wires, or traces, traverse these substrates to connect the silicon die to the external world. As data transmission rates have climbed from 56 Gigabits per second (Gbps) Non-Return-to-Zero (NRZ) to 112G and now 224G PAM4 (Pulse Amplitude Modulation 4-level), the physics of copper transmission lines begins to break down catastrophically.

This breakdown is primarily driven by the Skin Effect. As the frequency of the electrical signal increases, the alternating current (AC) density distributes itself non-uniformly within the conductor. The current is forced to flow only on the outer surface (or "skin") of the copper wire, exponentially reducing the effective cross-sectional area available for electron flow. This phenomenon causes the resistance of the conductor to skyrocket at high frequencies. At 224 Gbps, the effective resistance is orders of magnitude higher than at DC or low frequencies.4

Simultaneously, the industry faces Dielectric Loss. The organic material surrounding the copper traces is not a perfect insulator. As the electromagnetic field oscillates at extremely high frequencies (approaching and exceeding 100 GHz), the dipoles within the resin material vibrate, absorbing electromagnetic energy and converting the signal into heat. This manifests as signal attenuation or "insertion loss." In standard organic substrates, insertion loss can exceed 3-4 dB per inch at 112 GHz. This means that a signal traveling just a few inches from a GPU to a front-panel connector degrades to the point of becoming indistinguishable from background noise.7

2.2 The 224G Limit and the DSP Tax

The industry has now reached the 224G Limit. At these speeds, electrical signals on organic substrates degrade so rapidly that they can barely traverse the distance required to exit the package. To compensate for this massive loss, engineers have been forced to implement complex remedial measures. The primary solution has been the inclusion of massive Digital Signal Processors (DSPs) and "retimers" along the signal path. These components act as repeaters, amplifying and cleaning the signal at regular intervals.

However, this solution imposes a severe "DSP Tax." These retimers are energy vampires. In modern AI clusters, it is estimated that between 30% and 40% of the total system power is consumed not by the actual computation (the matrix multiplications performed by the GPU), but simply by the I/O circuits required to move data between chips.8 This power overhead generates massive amounts of waste heat, further complicating the thermal management of already dense server racks.

2.3 The Energy Crisis in AI Clusters

The implications of the copper barrier are most acute in the realm of Generative AI. Training a trillion-parameter model, such as GPT-5 or its successors, requires thousands of GPUs to function as a single, cohesive supercomputer. This architecture necessitates massive "East-West" traffic—data moving horizontally between GPUs within a rack and across racks.

Using traditional copper-based electrical interconnects or conventional pluggable optical modules results in an energy consumption profile of approximately 15–20 pJ/bit.3 While 15 picojoules may appear trivial in isolation, the math of scale reveals the crisis. When multiplied by 100 Terabits per second of bandwidth across a cluster of 10,000 GPUs, the power consumption attributed solely to data movement reaches hundreds of Megawatts. This creates a "Power Wall" that threatens to halt the economic and physical scaling of AI. A data center cannot simply consume infinite power; utility constraints and cooling physics impose hard caps.

The Intel-TSMC breakthrough targets this metric with aggressive precision. By switching to glass substrates and CPO, the alliance aims to bring the energy cost of data movement down to <5 pJ/bit. This effectively triples the energy efficiency of future AI data centers, allowing for larger models to be trained within the same power envelope.3

3. The Glass Revolution: Why Silicon is Switching to Glass

The solution announced by Intel and TSMC centers on the abandonment of organic substrates in favor of Glass Core Substrates. Glass is not merely a replacement material; it is a platform shift that enables manufacturing capabilities and performance metrics previously considered impossible in semiconductor packaging.

3.1 Material Superiority: Stiffness and Flatness

The primary driver for the adoption of glass is dimensional stability, specifically stiffness (Young's Modulus) and flatness. Organic substrates are inherently flexible and prone to warping during the high-heat reflow processes used to attach chips. As chip packages have grown larger—exceeding 100mm x 100mm to accommodate more High Bandwidth Memory (HBM) and compute tiles—this warpage has become a yield-killing defect. A warped substrate results in poor contact between the chip and the board, leading to electrical opens or shorts.

Glass substrates offer a transformative advantage in this regard. Glass is incredibly stiff and maintains its flatness even under thermal stress.

* Lithography Precision: The extreme flatness of glass allows for panel-level lithography with a very high depth-of-focus. In photolithography, if the surface is uneven, the focus of the light pattern blurs, limiting how small the features can be. The flatness of glass enables the printing of much finer lines and spaces. Intel reports that glass substrates enable a 10x increase in interconnect density compared to organic substrates. This allows for tighter packing of chiplets and more I/O pathways per square millimeter.1

* Warpage Control: Glass substrates exhibit 50% less pattern distortion and significantly reduced warpage. This stability is critical for the massive, multi-reticle packages required by next-generation GPUs like NVIDIA’s Rubin and AMD’s MI400, which integrate dozens of separate silicon dies.10

3.2 Through-Glass Vias (TGV): The Vertical Highway

The functional magic of the glass substrate lies in Through-Glass Vias (TGVs). These are microscopic vertical tunnels drilled through the glass core, typically using Laser Induced Deep Etching (LIDE) or advanced electrical discharge techniques, and then filled with copper.

* Signal Integrity: Glass is an excellent electrical insulator with a very low dielectric constant and loss tangent. Signals traveling through TGVs or the Redistribution Layers (RDL) built on top of the glass experience significantly less attenuation than in organic materials. This preserves signal integrity at high frequencies (hundreds of GHz), which is essential for supporting 224G and future 448G signaling standards without excessive power consumption.12

* Density and Pitch: TGVs can be placed much closer together than the Through-Hole Vias (THVs) used in organic cores. This allows for massive parallel I/O, solving the "beachfront" problem where there is insufficient edge space on a chip to route data out. High-density TGV arrays allow signals to escape vertically from anywhere under the chip, not just the edges.10

3.3 The Intel-TSMC Convergence and Standardization

Until this historic joint release, Intel and TSMC were pursuing parallel but distinct paths regarding advanced substrates.

* Intel: Has been pioneering glass substrate R&D for over a decade at its Assembly and Test Technology Development (ATTD) factories in Chandler, Arizona. Their focus was largely on the "Glass Core" itself as a superior mechanical foundation to support massive System-in-Package (SiP) designs and extend Moore's Law.1

* TSMC: Focused on the integration of photonics through its COUPE (Compact Universal Photonic Engine) platform, leveraging its CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging technology to integrate optical engines.2

The "Joint Release" signifies a critical standardization of the interface between the Glass Core and the Photonic Engine. This interoperability implies that a glass substrate manufactured by a third-party specialist (like Absolics or Corning) could theoretically host a TSMC-fabricated compute die and a Broadcom optical engine, all connected via a standardized high-speed protocol. This de-risks the technology for the entire ecosystem, moving it from proprietary experiments to a unified industry standard.

4. Co-Packaged Optics (CPO): The Architecture of Light

While the glass substrate provides the stable, high-speed foundation, Co-Packaged Optics (CPO) is the vehicle for the speed revolution. CPO represents the third and most radical phase of optical evolution in the data center, fundamentally changing how light is used to transmit information.

4.1 The Evolution: From Pluggables to CPO

The transition to CPO is the culmination of a clear evolutionary path driven by the need to reduce the distance electrical signals must travel before being converted to light.

1. Pluggable Optics (The Incumbent): Currently, optical transceivers (like QSFP-DD or OSFP modules) plug into the front panel of a switch or server rack. Electrical signals must travel from the GPU or switch ASIC, through the package, across several inches of PCB, to the connector at the front panel. Flaw: This long electrical path incurs high loss, necessitating power-hungry DSPs to drive the signal.

2. Near-Packaged Optics (NPO): A transitional step where optical modules are moved from the front panel onto the main PCB, surrounding the host ASIC. This shortens the electrical trace but still relies on distinct, separate modules. Status: A bridge technology that offers some benefits but retains significant complexity.

3. Co-Packaged Optics (CPO): The optical engine is moved inside the package, sitting on the same substrate (now Glass) as the GPU/Switch ASIC. Advantage: The electrical path is shortened from inches to millimeters. This drastic reduction eliminates the need for high-power retimers and DSPs, allowing the system to drive the optics with simple, low-power linear drivers. This is the only architecture capable of breaking the 5 pJ/bit barrier.6

4.2 TSMC's COUPE Architecture

TSMC's COUPE (Compact Universal Photonic Engine) is the specific implementation technology that will drive the 2026 mass production roadmap. COUPE is a 3D-stacked photonic integrated circuit (PIC) platform designed to maximize bandwidth density and energy efficiency.

* 3D Stacking: COUPE utilizes TSMC’s SoIC (System on Integrated Chips) technology to stack the Electronic Integrated Circuit (EIC) directly on top of the Photonic Integrated Circuit (PIC). The EIC contains the electrical drivers and control logic, while the PIC contains the modulators and waveguides. This "bumpless" hybrid bonding technique creates an extremely low-impedance connection between the electronics and the photonics, minimizing parasitic capacitance and inductance.

* The Glass Interposer: This integrated COUPE block is then mounted onto the Glass Substrate. The glass substrate's superior optical properties allow for advanced optical coupling. Waveguides—channels for light—can be embedded directly into the glass, or optical fibers can be aligned with micron-level precision using etched grooves in the glass. This precise alignment is critical for minimizing coupling loss—the amount of light lost when transferring between the fiber and the chip.16

* Energy Efficiency: By integrating the EIC and PIC so closely and removing the PCB trace, TSMC claims COUPE can reduce laser power consumption by over 40% and increase bandwidth density by 23x compared to traditional solder-bump based solutions.18

4.3 The "Hybrid" Advantage and Ecosystem Implications

The "Hybrid" aspect of the Intel-TSMC announcement likely refers to the mixing of best-in-class technologies to overcome manufacturing hurdles. Intel has historically led in substrate material science, specifically the processing of the glass core itself. TSMC leads in 3D silicon stacking (CoWoS/SoIC). A standardized ecosystem allows a chip designer (like NVIDIA) to utilize TSMC's COUPE optical engines mounted on a glass substrate that meets Intel's mechanical specifications.

This solves a major bottleneck: yield. Glass is brittle and difficult to manufacture at large panel sizes (510mm x 515mm) without breakage. By standardizing the interface, the industry can rely on specialist glass suppliers (like Corning or Absolics) to provide the reliable substrate panels, while foundries focus on the active silicon. This separation of concerns de-risks the technology for the entire ecosystem, allowing for a more robust supply chain.19

5. The Ecosystem War: LPO vs. CPO and the 2026 Inflection

While CPO is the ultimate destination, the industry is currently embroiled in a heated debate over the best route to get there. A transitional technology known as Linear Drive Pluggable Optics (LPO) has emerged as a strong contender for the 2024-2025 timeframe, creating a "Pluggable vs. CPO" war that defines the current investment landscape.

5.1 The LPO Argument (The Bridge)

LPO attempts to solve the power problem of pluggables without the radical packaging redesign of CPO. It removes the DSP from the pluggable module, relying instead on the linearity of the host ASIC's SerDes (Serializer/Deserializer) to drive the signal directly.

* Pros: LPO offers power savings of approximately 50% compared to DSP-based pluggables and significantly lowers latency. Crucially, it uses the same QSFP-DD or OSFP form factors, meaning data centers do not need to replace their existing rack infrastructure.

* Cons: LPO requires a very clean channel. As speeds increase to 224G, the signal degrades so much over the PCB trace that the host ASIC may struggle to drive it without a DSP. This limits the reach and robustness of LPO.21

5.2 Why CPO Wins in 2026

The Intel-TSMC announcement serves as a decisive signal that LPO is merely a stopgap technology. For AI Clusters operating at scale (10,000+ GPUs), LPO hits a hard wall at 3.2T and beyond.

* Density: LPO cannot match the bandwidth density of CPO. A CPO package can offer 100 Tbps of edge bandwidth. Achieving this with pluggable modules would require a front panel larger than the server rack itself. CPO enables "radix" (connectivity) scales impossible with front-panel plugs.3

* The NVIDIA/AMD Factor: Both major GPU vendors are aligning their 2026/2027 roadmaps (NVIDIA Rubin, AMD MI400/Helios) with CPO. The sheer density of compute in these racks—projected to exceed 120kW per rack—leaves no physical room for thousands of front-panel cables. The optics must move inside the package to free up space for cooling and power delivery.23

The "Joint Release" effectively deprecates LPO for flagship AI designs post-2026. It signals to the supply chain: "Stop optimizing for copper traces; start building for glass." The industry is moving from an era of incremental improvements to one of architectural revolution.

6. Supply Chain & Manufacturing: The New "Glass" Tier

The shift to glass creates an entirely new tier in the semiconductor supply chain. This is no longer just about foundries; it is about materials science and panel-level processing. The manufacturing of glass substrates involves different physics and machinery than silicon wafers or organic PCBs, creating opportunities for new market leaders.

6.1 The Glass Barons: Corning, Schott, Absolics

The substrate itself is the new battleground.

* Absolics (SKC Subsidiary): Currently the leader in commercialization. Their plant in Covington, Georgia, is the first large-scale glass substrate facility, funded partially by the US CHIPS Act. They are targeting mass production by late 2025, aligning perfectly with the Intel-TSMC 2026 window. Absolics uses a proprietary processing technology to ensure the durability of the glass during the drilling of TGVs.26

* Corning: Leveraging their vast expertise in display glass (Gorilla Glass, LCD substrates), Corning is positioning its "fusion draw" process to create ultra-flat glass panels for semiconductors. This process creates pristine surfaces without the need for polishing, a significant cost advantage. They forecast the glass substrate market to reach $10 billion by 2026.28

* Schott: Offering structured glass with pre-drilled TGVs, positioning themselves as a high-precision supplier. Their "Hermae" glass and other specialized compositions are targeted at RF and 5G applications alongside AI, offering extremely low dielectric loss.29

6.2 The CPO Engine Builders: Broadcom, Marvell, Lightmatter

While TSMC builds the structure, companies like Broadcom and Marvell build the engines—the optical chiplets that do the actual work.

* Broadcom: The clear market leader in data center switching. Their "Bailly" CPO switch is already in its second generation. Broadcom is driving the 200G/lane and 400G/lane standards that will utilize the glass highway. Their strategy is to offer a complete CPO ecosystem, including the switch ASIC, the optical engine, and the fiber connectors.31

* Marvell: Focusing on "cloud-optimized" CPO with their Teralynx platform. Their strategy emphasizes interoperability and open standards to combat Broadcom's dominance. Marvell is integrating CPO capability directly into its custom ASICs for hyperscalers like Google and Amazon.32

* Lightmatter: The disruptor. Their "Passage" technology is a programmable photonic interconnect that functions as a "wafer-scale" computer. Their 3D photonic superchip (M1000) could theoretically bypass the need for traditional switching altogether by weaving connectivity directly into the compute layer. This represents the most radical vision of the CPO future, where the network and the computer become indistinguishable.34

7. Standards: UCIe and OIF as the Lingua Franca

The "Joint Release" relies heavily on two standards bodies to ensure this new hybrid ecosystem functions: UCIe (Universal Chiplet Interconnect Express) and OIF (Optical Internetworking Forum). Without these standards, the industry would fragment into incompatible proprietary fiefdoms.

* UCIe: This is the protocol that allows the GPU chiplet to talk to the Optical Engine chiplet on the glass substrate. The Intel-TSMC announcement likely includes a UCIe-Optical extension, standardizing the physical layer (PHY) for optical I/O. This means an NVIDIA GPU could talk to a Broadcom Optical Engine over a TSMC-packaged link without friction. UCIe allows for mix-and-match chiplet integration, enabling a marketplace of compatible components.36

* OIF and the External Laser Source (ELS): A key challenge of CPO is that lasers degrade rapidly in high heat. If the laser is placed inside the hot GPU package (which can reach 100°C), its lifespan is drastically reduced. The OIF is defining the ELSFP (External Laser Small Form Factor Pluggable) standard. This allows the laser source to remain external (pluggable on the front panel) while the modulator (the part that encodes data) sits on the hot glass package. This "remote light source" approach transmits "dumb" continuous wave light via fiber to the GPU, where it is modulated. If the laser burns out, a technician simply replaces the $500 laser module on the front panel, rather than discarding the $50,000 GPU package. This standard is critical for the reliability and serviceability required by hyperscalers.38

8. Strategic Roadmaps: NVIDIA Rubin and AMD Helios

The timing of the Intel-TSMC announcement (late 2025) is perfectly calibrated to support the next generation of AI flagships. The specifications released are not abstract; they are the blueprints for the supercomputers of 2027.

8.1 NVIDIA Rubin (2026/2027)

NVIDIA's roadmap reveals the "Rubin" architecture, the successor to the Blackwell platform. Rubin is designed for the "Glass Era."

* Specs: Rubin Ultra aims for massive rack-scale integration, potentially housing 576 GPUs in a single rack-scale system. This density is physically impossible with copper interconnects due to cable bulk and signal loss.

* The Pivot: NVIDIA's NVLink 6.0 is expected to transition from electrical to optical for rack-scale communication. The glass substrate will be the physical carrier for this optical mesh, allowing the GPU to drive optical signals directly into the NVLink fabric. This enables a "flat" network topology where every GPU can talk to every other GPU with minimal latency.23

8.2 AMD MI400 and Helios (2026)

AMD is aggressively pursuing "rack-scale" design with its Helios platform.

* Architecture: Helios combines EPYC processors and MI400 GPUs into a unified system. The MI400 is rumored to feature up to 12 HBM4 stacks and a new iteration of Infinity Fabric.

* The Glass Angle: AMD has been a first-mover in chiplet technology (with TSMC). The transition to glass substrates allows them to place more HBM stacks and optical engines side-by-side without the package warping. The superior flatness of glass is essential for the reliable bonding of these massive chiplet arrays.24

9. Investment & Market Outlook: The 2026-2030 Boom

The convergence of Glass Substrates and CPO creates a high-growth investment thesis for 2026 and beyond. The semiconductor market is pivoting its focus from "Front-end" (transistor scaling and lithography) to "Back-end" (advanced packaging and interconnects). Value is migrating from the wafer to the package.

9.1 Market Forecasts

* CPO Market: Expected to grow at a Compound Annual Growth Rate (CAGR) of 37-46% from 2026 to 2036, exceeding $20 billion by 2036. The initial ramp in 2026 will be driven almost exclusively by hyperscalers (Google, Meta, AWS, Microsoft) upgrading their AI training clusters to the next generation of efficiency.41

* Glass Substrate Market: Projected to reach $10-12 billion by 2035, growing from a niche status today to a mainstream material for High-Performance Computing (HPC). As the technology matures and costs decrease, glass is expected to trickle down from AI supercomputers to high-end consumer electronics.28

9.2 Winners and Losers

* Winners (The "Pick and Shovel" Plays):

* Substrate/Material Suppliers: Corning (GLW) and Absolics (SKC) are best positioned to capture the value of the substrate itself. Their proprietary glass formulations and processing techniques create a moat.

* CPO Leaders: Broadcom (AVGO) and Marvell (MRVL) dominate the DSP and Optical Engine market. They provide the essential silicon that makes the glass substrate useful.

* Advanced Packaging Foundries: TSMC (TSM) retains the crown for integration, but Intel (INTC) has a unique opportunity to monetize its glass expertise as a merchant foundry service (IFS), potentially serving customers who use TSMC for wafers but Intel for packaging.

* At Risk:

* Traditional PCB Makers: Manufacturers relying solely on organic substrates (ABF) for high-end markets face commoditization as the "premium" tier moves to glass. They must innovate or be relegated to lower-margin markets.

* Legacy Pluggable Optics Vendors: Companies slow to pivot from QSFP modules to CPO engines risk obsolescence in the AI server market. The value is moving inside the switch/GPU package, cutting out the external module makers.

10. Conclusion: The Glass Ceiling Shattered

The joint 2026 milestone from Intel and TSMC is more than a simple specification release; it is the industry's collective admission that copper has reached its physical limit. The transition to the Silicon-Glass Hybrid platform solves the most pressing bottleneck in the AI era: the prohibitive energy cost of moving data.

By 2027, the standard "AI Superchip" will not be a silicon die sitting on a plastic board. It will be a complex, 3D-stacked metropolis of compute and memory, resting on a sheet of glass, communicating with the world through pulses of light. For investors, engineers, and strategists, the message is unambiguous: The future of AI infrastructure is transparent, rigid, and optical. The Glass Era has begun.

Detailed Analysis of Key Technologies & Trends

The Technical "Why": Deep Dive into Signal Physics

To truly grasp the necessity of this shift, one must look at the Shannon-Hartley theorem and the Nyquist limit. As we push data rates higher, we require more bandwidth. In copper, bandwidth is strictly limited by frequency-dependent attenuation.

* Insertion Loss: At 112 GHz (the Nyquist frequency for 224 Gbps PAM4), a standard PCB trace loses over 3-4 dB per inch. A 10-inch trace loses 30-40 dB, rendering the signal undetectable without massive amplification.

* Glass Advantage: Glass has a tunable dielectric constant (Dk) and Loss Tangent (Df) that are significantly lower than organic build-up films (ABF). This reduces insertion loss, extending the "reach" of the signal or reducing the power needed to drive it.

Thermal Management: The Hidden Benefit

Glass has another trick: Thermal Conductivity. While glass itself is a thermal insulator, the ability to drill dense copper TGVs allows the substrate to act as a heat pipe, wicking heat away from the hot GPU die more effectively than organic cores. This is critical as GPUs push past 1000W TDP (Thermal Design Power).13

The Serviceability Challenge

One major hurdle remains: Serviceability. If a laser fails in a CPO package, you cannot simply "unplug" it like a transceiver. You might have to discard the whole $50,000 GPU.

* Solution: The industry is coalescing around the External Laser Source (ELS) model (OIF standard). The laser—the component most likely to fail due to heat degradation—is kept in a pluggable module on the front panel. It sends "dumb" continuous wave light via fiber to the GPU. The GPU's modulator (on the glass substrate) chops this light to encode data. If the laser burns out, you just replace the $500 laser module, not the GPU.38

This elegant compromise—pluggable lasers, integrated modulators—is the key that unlocks CPO reliability for mass deployment in 2026. The industry has solved the physics, the manufacturing, and the reliability challenges. Now, it is time to build.